1. Field of Invention
The present invention relates to non-volatile memory devices, and methods for making such devices.
2. Description of the Related Art
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells or a sector of cells in the device at once.
As with many types of semiconductor devices, requirements for increases in device density to increase speed of operation for integrated circuit devices and/or to reduce their cost, have led to a desire for decreased size of individual components of non-volatile memory devices, such as cells of memory devices.
According to an aspect of the invention, a non-volatile memory device includes a semiconductor substrate, wherein the substrate has a pair of trenches therein; a tunnel oxide on a top substrate surface of the substrate; a pair of insulators, wherein the insulators have respective lower trench-fill portions in respective of the trenches, wherein the insulators have respective upper protruding portions protruding from the top substrate surface, and wherein the upper protruding portions have respective top insulator surfaces; a floating gate over the tunnel oxide and between the upper protruding portions, wherein the floating gate is in contact with both of the upper protruding portions; an interpoly dielectric over the floating gate, wherein the interpoly dielectric is in contact with the floating gate; and a control gate over the interpoly dielectric, wherein the control gate is in contact with the control gate.
According to another aspect of the invention, a non-volatile memory device includes a semiconductor substrate, wherein the substrate has a pair of trenches therein; a tunnel oxide on a top substrate surface of the substrate; a pair of insulators, wherein the insulators have respective lower trench-fill portions in respective of the trenches, wherein the insulators have respective upper protruding portions protruding from the top substrate surface, and wherein the upper protruding portions have respective top insulator surfaces; a floating gate over the tunnel oxide and between the upper protruding portions, wherein the floating gate is in contact with both of the upper protruding portions; an interpoly dielectric over the floating gate, wherein the interpoly dielectric is in contact with the floating gate; and a control gate over the interpoly dielectric, wherein the control gate is in contact with the control gate. A top gate surface of the floating gate is at substantially the same distance from the top substrate surface as the top insulator surfaces. The interpoly dielectric is substantially planar, thereby being a substantially constant distance from the top substrate surface. The control gate is also substantially planar. The interpoly dielectric includes upper and lower layers, with a middle layer therebetween. The floating gate and the protruding portions provide a continuous lower surface for the interpoly dielectric, thereby preventing the interpoly dielectric from contacting the tunnel oxide.
According to a further aspect of the invention, a method of making a non-volatile memory device includes forming a pair of insulators on a substrate, the insulators each having an upper protruding portion that protrudes from a top substrate surface of the substrate; forming a floating gate between the upper protruding portions, wherein the control gate is in contact with both of the upper protruding portions; forming an interpoly dielectric on the floating gate and the upper protruding portions; and forming a control gate on the interpoly dielectric.